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Application:
CORE
Program Memory Wait States
Set to zero for fast memory.
Data Memory Wait States
Set to zero for fast memory.
Bus State Status — Read Only
0 = DSP NOT a Bus Master
1 = DSP a Bus Master
Bus Request Hold
0 = BR Asserted By External Access
1 = BR Always Asserted
Port A
Bus Control Register (BCR)
X:$FFDE Read/Write
Reset = $43FF
Carry
Overflow
Zero
Negative
Unnormalized
Extension
Limit
Sticky Bit
Interrupt Mask
Scaling Mode
ForeVer Flag
Loop Flag
Status Register (SR)
Read/Write
Reset = $0300
= Reserved, Program as zero
*
C - 18
DSP56156 Core Programming Sheet
15 14 13 12 11 10 9
* * * *
RH
BS
1
0
Figure C-2 Bus Control Register (BCR)
15 14 13 12 11 10 9
* *
LF
FV
0
Figure C-3 Status Register (SR)
PROGRAMMING SHEETS
Date:
Programmer:
8
7
X4
X3
X2
X1
0
0
0
= Reserved, Program as zero
*
8
7
S1
S0
I1
I0
S
0
MR
Sheet 1 of 3
6
5
4
3
2
1
0
X0
P4
P3
P2
P1
P0
6
5
4
3
2
1
L
E
U
N
Z
V
CCR
MOTOROLA
0
C
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