Transmit Slot Mask Shift Register - Tsms; Receive Slot Mask Registers - Rsmax And Rsmbx - Motorola DSP56156 Manual

The 32-bit data written into TSMx is transferred to the Transmit Slot Mask Shift Register
(TSMS) during the last slot of the last frame. Writing to TSMx will not affect the state of
the active (enabled) transmit slots during the current transmit frame but only that of the
next frame.
Using the slot mask in TSMx does not conflict with using TSR. Even if a slot is enabled in
TSMx, the user may choose to write to TSR instead of writing to the transmit data register
TX. This will cause the transmit data pin to be three-stated during the next slot.
After DSP reset, the Transmit Slot Mask Register is preset to $FFFFFFFF, which means
that all 32 possible slots are enabled for data transmission.
Note: The Transmit Slot Mask Registers have to be written before the last three serial
clock cycles of a frame in order to become active at the beginning of the next frame.
8.16

TRANSMIT SLOT MASK SHIFT REGISTER - TSMS

The Transmit Slot Mask Shift Register is a 32-bit shift register. At the end of each frame,
it is loaded with the 32-bit mask from TSM. Then, it is shifted one bit to the right near the
end of each transmitted word. The LSB of TSMS is used as an enable/disable for trans-
mitting data to the transmit data pin (STD) and setting the TDE flag after transmitting data.
This register is not accessible to the programmer.
8.17

RECEIVE SLOT MASK REGISTERS - RSMAx AND RSMBx

The Receive Slot Mask Registers are two 16-bit read/write registers. They are used by
the receiver in network mode to determine for each slot whether to receive a data word
and generate a receiver full condition (RDF=1), or to ignore the received data. RSMAx
and RSMBx should be seen as only one 32-bit register RSMx. Bit number N in RSMx is
an enable/disable control bit for receiving data in slot number N.
When bit number N in RSMx is cleared, the data from the receive data pin is shifted into
the Receive Shift Register during slot number N. Data is not transferred from the Receive
Shift Register to the Receive Data Register and the Receiver Full flag (RDF) is not set.
Also the Receiver Overrun Error flag is not set. This means that during a disabled slot, no
Receiver Full interrupt is generated. The DSP is interrupted (RDF=0). The DSP is inter-
rupted by activity in enabled slots only.
When bit number N in RSMx is set, the receive sequence is as usual: data which is shifted
into the receive shift register is transferred to the Receive Data register and the RDF flag
is set.
MOTOROLA SYNCHRONOUS SERIAL INTERFACE (SSI0 and SSI1)
TRANSMIT SLOT MASK SHIFT REGISTER - TSMS
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