Example 5 - Real-Time I/O Example With On-Chip Codec And Pll - Motorola DSP56156 Manual

6.6.5 Example 5 — Real-Time I/O Example with On-Chip Codec and PLL
The routine in this example performs real-time input-output for the main DSP routine. As
mentioned, the DSP56156 has an on-chip A/D and D/A codec which allows the DSP to
communicate with a microphone and a speaker directly. Thus, the set-up sequences for
the codec as well as the on-chip frequency synthesizer (PLL) are included. There are sev-
eral registers to be set before they are used, such as Bus Control Register (BCR), Inter-
rupt Priority Register (IPR), Operating Mode Register (OMR), Codec Control Register
(COCR), and PLL Control Register (PLCR). The operational functions for this routine are:
1. Read the comb filter output of the on-chip A/D converter (the comb filter performs
the low pass filtering with 125:1 decimation).
2. Perform a 2:1 decimation low pass filter using a 4th-order IIR filter structure.
3. Test the result and save current data for the next interpolation filter section. The
main routine can be called at this time.
4. Obtain the output data for the D/A converter or repeat the last output sample for
2:1 interpolation.
5. Run a 1:2 interpolation low pass filter routine using a 4th-order IIR filter.
6. Write the interpolation filter output to the on-chip D/A comb filter section which per-
forms a 1:125 interpolation low pass filter. Note that this routine uses interrupt driv-
en I/O and the master clock for the DSP56156 is synthesized by the PLL circuitry.
;************************************************************************************************************
; Real-Time I/O routine
;
; Fext = 32Mhz and plcr = #$4f as an example
; DSP master clock Fosc = 32/(15+1)x4x(6+1)=56MHz
; Codec Clock 2MHz = 32M/16
; Codec output rate 8KHz (125:1 and 2:1 decimation with 2MHz)
;
; Note: 1. Interrupt driven codec routine
; 2. Master clock is driven from PLL
;************************************************************************************************************
;
opt cc,mu,now
nstages equ 4
Nc equ 4*nstages+1
Nw equ 2*nstages
start equ $40
cocr equ $ffc8
ctx equ $ffe9
crx equ $ffe9
cosr equ $ffe8
plcr equ $ffdc
ipr equ $ffdf
6 - 62
APPLICATION EXAMPLES
;number of IIR stages
;include room for gain
;memory requirement for filter states
;Start address for the program
;Codec control register
;Codec transmit data reg
;Codec receive reg
;Codec status register
;Pll control register
;Interrupt Priority Register
DSP56156 ON-CHIP SIGMA/DELTA CODEC MOTOROLA