Introduction - Motorola DSP56156 Manual

INTRODUCTION

5.1

INTRODUCTION

The Host Interface (HI) is a byte-wide parallel slave port which may be connected directly
to the data bus of a host processor. The host processor may be any of a number of popular
microcomputers or microprocessors, another DSP or DMA hardware. The DSP56156 has
an 8-bit bidirectional data bus H0-H7 (PB0-PB7) and 7 control lines HR/W, HEN, HREQ,
HA0-HA2, and HACK (PB8-PB14) to control data transfers. The HI pin functions are de-
scribed in Section 2. The HI appears as a memory mapped peripheral, occupying 8 bytes
in the host processor's address space and three words in the DSP processor's address
space. Figure 5-1 shows the HI block diagram. Separate transmit and receive data regis-
ters are double-buffered to allow the DSP56156 and host processor to efficiently transfer
data at high speed. Host processor communication with the HI registers is accomplished
using standard host processor instructions and addressing modes. Host processors may
use byte move instructions to communicate with the HI registers. The host registers are
addressed so that 8-bit MC6801-type host processors can use 16-bit load (LDD) and store
(STD) instructions for data transfers. The 16-bit MC68000/10 host processor can address
the HI using the special MOVEP instruction for word (16-bit) or long word (32-bit) trans-
fers. The 32-bit MC68020 host processor can use its dynamic bus sizing feature to ad-
dress the HI using standard MOVE word (16-bit), or long word (32-bit) instructions.
Handshake flags are provided for polled or interrupt-driven data transfers. The DSP56156
interrupt response is sufficiently fast that most host microprocessors can load or store
data at their maximum programmed I/O (non-DMA) instruction rate without testing the
handshake flags for each transfer. If the full handshake is not needed, the host processor
can treat the DSP56156 as fast memory and data can be transferred between the host
and DSP56156 at the fastest host processor rate. DMA hardware may be used with the
external Host Request and Host Acknowledge pins to transfer data at the maximum
DSP56156 interrupt rate.
The host processor can also issue vectored exception requests to the DSP56156 with the
host command feature. The host may select any of the 32 DSP exception routines to be
executed by writing a vector address register. This flexibility allows the host programmer
to execute a wide number of preprogrammed functions inside the DSP56156. Host excep-
tions can allow the host processor to read or write DSP56156 registers, Data memory or
Program memory locations and perform control and debugging operations if exception
routines are implemented in the DSP to do these tasks.
The DSP56156 CPU views the HI as a memory mapped peripheral occupying three 16-bit
words in data memory space. The DSP56156 may access the HI as a normal memory-
mapped peripheral using standard polled or interrupt programming techniques.
MOTOROLA HOST INTERFACE 5 - 3