Motorola DSP56156 Manual page 262

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PLCR
Before turning the PLL off, the PLLE bit should be cleared in order to by-pass the PLL.
The PLL can then be put in the power down mode by setting PLLD.
If the PLL output frequency has to be changed by re-programming the ED and/or YD bits
while the PLL output is used by the core (PLLE=1;PLLD=0), the following sequence
should be performed:
• clear PLLE bit to switch back to EXTAL
• program YD and/or ED bits (only after clearing PLLE)
• wait for the LOCK bit to be set
• set PLLE after the LOCK bit is set
9.3.7 PLCR Voltage Controlled Oscillator Lock Bit (LOCK) Bit 15
This status bit indicates if the Voltage Controlled Oscillator (VCO) has locked on the
desired frequency or not. When the LOCK bit is set, the VCO has locked; when the
LOCK bit is cleared, the VCO has not locked yet. This bit is cleared by setting the PLLD
bit and by changing the value of ED or YD. The LOCK bit is not cleared when clearing
the PLLE bit unless PLLD, YD, and ED are also changed. This bit is read-only and can-
not be written by the DSP core.
9.3.8 PLCR Reserved Bits (Bits 8-9,12)
These bits are reserved and should be written as zero by the user. They read as a logic
zero.
MOTOROLA
Table 9-2 PLL Operations
PLLE PLLD Fosc
0 0 EXTAL
0 1 EXTAL
1 0 PLLout
1 1
ON-CHIP FREQUENCY SYNTHESIZER
PLL Mode
Active
Power Down
Active
reserved
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