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three words in the DSP processor's address space. Separate transmit and receive data
registers are double-buffered to allow the DSP56156 and host processor to efficiently
transfer data at high speed. Host processor communication with the HI registers is accom-
plished using standard host processor instructions and addressing modes. Host proces-
sors may use byte move instructions to communicate with the HI registers. The host
registers are addressed so that 8-bit MC6801-type host processors can use 16-bit load
(LDD) and store (STD) instructions for data transfers. The 16-bit MC68000/10 host pro-
cessor can address the HI using the special MOVEP instruction for word (16-bit) or long
word (32-bit) transfers. The 32-bit MC68020 host processor can use its dynamic bus siz-
ing feature to address the HI using standard MOVE word (16-bit), long word (32-bit) or
quad word (64-bit) instructions.
One of the most innovative features of the HI is the Host Command feature. With this fea-
ture, the host processor can issue vectored exception requests to the DSP56156. The
host may select any one of 31 DSP56156 exception routines to be executed by writing a
Vector Address Register in the HI. This flexibility allows the host programmer to execute
up to 31 functions preprogrammed in the DSP56156.
1.5
OnCE
OnCE provides hardware/software emulation and debug on the DSP56156 and a means
of interacting with the DSP56156 and any memory mapped peripherals non-intrusively so
that a user may examine registers, memory, or on-chip peripherals. To achieve this, spe-
cial circuits and dedicated pins on the DSP are used to avoid sacrificing any user acces-
sible on-chip resource. A key feature of the special OnCE pins is to allow the user to insert
the DSP56156 into his target system yet retain debug control, especially in the cases of
devices specified without external bus. The need for a costly cable which brings out the
all processor pins on traditional emulator systems is eliminated.
1.6
PROGRAMMING MODEL
The programmer can view the DSP56156 architecture as three execution units operating
in parallel. The three execution units are the Data ALU, Address Generation Unit, and Pro-
gram Control Unit. The programming model appears like that of a conventional MPU. The
programming model is shown in Figure 1-10 and is described in the following paragraphs.
1.6.1
Data ALU
The data ALU features four 16-bit input/output data registers which can be concatenated
to handle 32-bit data, two 40-bit accumulators, automatic scaling, and saturation arith-
metic.
MOTOROLA
OnCE
DSP56156 OVERVIEW
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