Data Alu Input Registers (X1, X0, Y1, Y0); Data Alu Accumulator Registers (A2, A1, A0, B2, B1, B0); Address Generation Unit; Address Register File (R0-R3) - Motorola DSP56156 Manual

1.6.1.1

Data ALU Input Registers (X1, X0, Y1, Y0)

X1, X0, Y1, and Y0 are 16-bit latches which serve as input pipeline registers for the data
ALU. Each register may be read or written by the XDB. X0, X1, and Y0 may be written
over the GDB. They may be treated as four independent 16-bit registers or as two 32-bit
registers called X and Y which are developed by the concatenation of X1:X0 and Y1:Y0
respectively. X1 is the most significant word in X and Y1 is the most significant word in Y.
These Data ALU input registers are used as source operands for most data ALU opera-
tions and allow new operands to be loaded for the next instruction while the register con-
tents are being used by the current instruction.
1.6.1.2

Data ALU Accumulator Registers (A2, A1, A0, B2, B1, B0)

A1, A0, B1 and B0 are 16-bit latches which serve as data ALU accumulator registers. A2
and B2 are 8-bit latches which serve as accumulator extension registers. Each register
may be read or written by the XDB as a word operand. A1 and B1 may be written by the
GDB. When A2 or B2 is read, the register contents occupy the low-order portion (bits 7-0)
of the word; the high-order portion (bits 16-8) is sign-extended. When A2 or B2 is written,
the register receives the low-order portion of the word; the high-order portion is not used.
Automatic sign extension of the 40-bit accumulators is provided when the A or B register
is written with a smaller size operand. If the A or B register is written with a 16-bit value,
then the least significant 16 bits are set to zero.
It is also possible to saturate the accumulator on a 32-bit value automatically after every
accumulation. Overflow protection is performed after the contents of the accumulator
have been shifted according to the scaling mode defined in the status register. When lim-
iting occurs, the L bit flag in the status register is set and latched.
1.6.2

Address Generation Unit

The programmer's model for the address generation unit consists of three banks of regis-
ter files — pointer register files, offset register files, and modifier register files. These pro-
vide all the registers necessary to generate address register indirect effective addresses.
1.6.2.1

Address Register File (R0-R3)

The Address Register File consists of four, sixteen-bit registers. The file contains the ad-
dress registers R0-R3 which usually contain addresses used as pointers to memory. Each
register may be read or written by the Global Data Bus. Each address register may be
used as an input to the modulo arithmetic unit for a register update calculation. Each reg-
ister may be written by the GDB or by the output of the modulo arithmetic unit.
MOTOROLA
PROGRAMMING MODEL
DSP56156 OVERVIEW 1 - 23