Off-Chip Memory Expansion; Internal Buses - Motorola DSP56303 User Manual

Internal Buses

1.5.7

Off-Chip Memory Expansion

Memory can be expanded off chip to the following capacities:
Data memory expansion to two 256 K 24-bit word memory spaces using the standard
external address lines
Program memory expansion to one 256 K
standard external address lines
Further features of off-chip memory include the following:
External memory expansion port
Simultaneous glueless interface to static random access memory (SRAM) and dynamic
random access memory (DRAM)
1.6 Internal Buses
To provide data exchange between the blocks, the DSP56303 implements the following
buses:
Peripheral I/O expansion bus to peripherals
Program memory expansion bus to program ROM
X memory expansion bus to X memory
Y memory expansion bus to Y memory
Global data bus between PCU and other core structures
Program data bus for carrying program data throughout the core
X memory data bus for carrying X data throughout the core
Y memory data bus for carrying Y data throughout the core
Program address bus for carrying program memory addresses throughout the core
X memory address bus for carrying X memory addresses throughout the core
Y memory address bus for carrying Y memory addresses throughout the core.
The block diagram in Figure 1-1 illustrates these buses among other components.
1-10
24-bit words memory space using the
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