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Operation
9.2.2
Timer Initialization
To initialize a timer, do the following:
1.
Ensure that the timer is not active either by sending a reset or clearing the TCSR[TE]
bit.
2.
Configure the control register (TCSR) to set the timer operating mode. Set the interrupt
enable bits as needed for the application.
3.
Configure other registers: Timer Prescaler Load Register (TPLR), Timer Load Register
(TLR), and Timer Compare Register (TCPR) as needed for the application.
4.
Enable the timer by setting the TCSR[TE] bit.
9.2.3
Timer Exceptions
Each timer can generate two different exceptions:
n
Timer Overflow (highest priority) — Occurs when the timer counter reaches the
overflow value. This exception sets the TOF bit. TOF is cleared when a value of one is
written to it or when the timer overflow exception is serviced.
n
Timer Compare (lowest priority) — Occurs when the timer counter reaches the value
given in the Timer Compare Register (TCPR) for all modes except measurement
modes. In measurement modes 4–6, a compare exception occurs when the appropriate
transition occurs on the
cleared when a value of one is written to it or when the timer compare interrupt is
serviced.
To configure a timer exception, perform the following steps. The example at the right of each
step shows the register settings for configuring a Timer 0 compare interrupt. The order of the
steps is optional except that the timer should not be enabled (step 2e) until all other exception
configuration is complete:
1.
Configure the interrupt service routine (ISR):
a.
Load vector base address register
b.
Define I_VEC to be equal to the VBA value (if that is nonzero). If it is defined,
I_VEC must be defined for the assembler before the interrupt equate file is
included.
c.
Load the exception vector table entry: two-word fast interrupt, or jump/branch to
subroutine (long interrupt).
9-4
signal. The Compare exception sets the TCF bit. TCF is
TIO
DSP56303 User's Manual
VBA (b23–8)
p:TIM0C
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