Figure 4-5 Refresh Timer Functional Diagram; Using The Internal Refresh Timer - Motorola DSP56009 User Manual

4.4.3

Using The Internal Refresh Timer

Refresh cycles can be periodically inserted by the EMI. The refresh cycle insertion
rate is controlled by the programmable refresh timer. The refresh activity is enabled
or disabled according to the EREF and ERED bits in the ERCR and refresh is active
only in the EMI DRAM operating modes, or in the concurrent SRAM mode where the
multiplexed pins are defined as CAS and RAS.
The EMI always completes its current operation and then checks for pending read or
write triggers. The refresh request has the highest priority, otherwise the channel
could be kept too busy by the user to ensure all of the DRAM data is refreshed.
The CAS before RAS refresh cycles are inserted between memory accesses when the
EMI controller is in its idle state and a refresh request has been delivered by the
refresh timer. The refresh request is internally reset at the end of the external refresh
cycle. The selected refresh cycle rate must take into account the DSP clock frequency
and the DRAM device refresh requirements.
The refresh timer block diagram is illustrated in Figure 4-5. The DSP clock is first
divided by a factor ranging between 1 and 256 (according to the ECD bits in ERCR),
and then by 1, 8, or 64 using a prescaler (selected by bits EPS[1:0]), to achieve the
required refresh rate.
F
OSC
(DSP Clock)

Figure 4-5 Refresh Timer Functional Diagram.

4.4.3.1 "On Line" Refresh
During initialization, the user should set the ECSR EDTM bit and the ERCR bits for
the required DRAM refresh cycle timing, refresh enable (EREF), and refresh rate.
After this the user does not have to consider refresh cycles, as the internal refresh
timer will continuously initiate refresh cycles at the programmed rate. Refer to
Section 4.4.5 for more details.
Note: Special attention should be given to cases in which data transfers are
performed when the DSP is not polling status bits or receiving EMI interrupts,
as the predetermined number of instruction cycles can change due to the
insertion of external refresh cycles.
MOTOROLA
Divider Prescaler
Divide by Divide by
1 to 256 1, 8, or 64
ECD[7:0]
DSP56009 User's Manual
External Memory Interface
Refresh Request Rate
EPS[1:0]
DRAM Refresh
AA0297k
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