Figure 4-8 Emi Pipeline - Motorola DSP56009 User Manual

• If an access is being processed (EBSY = 1), an additional trigger can be
generated. This trigger will be considered pending if:
– the address calculation is executed overlapping the last I
access, and/or
– the external access immediately follows, thus providing full bus
bandwidth.
• EBAR is incremented and updated (if EINR = 1 for read, or EINW = 1 for
write) one I
cyc
• Following a read access, the data is available on EDRR, and can be read by the
DSP core:
– SRAM modes—at the first I
– Fast DRAM mode—at the last I
– Slow DRAM mode—at the I
Special consideration should be given when triggering a new access after two read
accesses since the EMI Data Register Buffer (EDRB) can be full if the EMI Data Read
Register (EDRR) is also full. In this case the new trigger will remain pending and the
new access will not take place until the EDRB is empty. The status of the EDRB can be
verified by checking the ECSR EBDF flag. If EBDF = 0 after a read operation, the
EDRB is empty and it is possible to start a new access immediately. Figure 4-8
illustrates the EMI pipeline.
I
I Flow
–1
cyc
trig1
Core Operation
EMI Operation
EBSY
External Access
MOTOROLA
after the address calculation time frame.
cyc
cyc
I 0 I I I
1 2 3
read
EBAR trig2
comp1 incr1

Figure 4-8 EMI Pipeline

DSP56009 User's Manual
External Memory Interface
EMI Operating Considerations
after completing the external access
of the external access
cyc
after the last I of the external access
cyc
IN–1 IN
Data Access # 1
of the current
cyc
IN+1 IN+2 IN+3
read
trig3
EDRR
comp2 incr2
Data Access # 2
AA0300k
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