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A.1
INTRODUCTION
This section presents the bootstrap programs (ROM code) contained in the DSP.
A.2
BOOTSTRAPPING THE DSP
The bootstrap ROM occupies locations 0–31 ($0–$1F) and 256–287 ($100–$11F) in two
areas in the bootstrap memory map. The bootstrap ROM is factory-programmed to
perform the bootstrap operation following hardware reset. It either jumps to the
user's ROM starting address (P:$2000), or downloads up to 512 words of user
program from an external EPROM attached to the EMI port or from the SHI port in
2
SPI or I
C formats. The bootstrap ROM activity is controlled by the MC:MB:MA bits
in the OMR. When in the Bootstrap mode, the first 512 words of Program RAM are
disabled for read, but accessible for write.
Programs are loaded from external EPROM if MC:MB:MA = 001. The internal
Program RAM is loaded with 1,536 consecutive bytes from an EPROM connected to
the EMI. The EPROM is located at the EMI address $0, when operating the EMI in the
Absolute Addressing SRAM mode (EAM2-EAM0 = 000). It is assumed that the
EPROM is selected (enabled) through the GPIO3 pin, which is driven low in this
Bootstrap mode. The GPIO3 output is programmed to be of the active high/active
low type. The bytes will be packed into 512 24-bit words and stored in contiguous
Program RAM memory locations starting at P:$0000.
Note: The routine loads data starting with the least significant byte of P:$0000.
Programs can be loaded from the SHI in the SPI mode if MC:MB:MA = 101, or in the
2
I
C mode if MC:MB:MA = 111. The internal Program RAM is loaded with 512 words
that are 24-bits long and are received through the SHI. The SHI operates in the Slave
mode, with the 10-word FIFO enabled, and with the HREQ pin enabled for receive
operation. The OnCE
The bootstrap program listing is shown on the following page.
MOTOROLA
TM
port is enabled by the bootstrap code.
DSP56009 User's Manual
Bootstrap ROM Contents
A-3
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