Motorola DSP56009 User Manual page 286

SPI Data-To-Clock Timing 5-10
SPI Data-To-Clock Timing Diagram 5-10
SPI Mode 5-3
SR (Status Register) B-14
SRAM Read/Write Timing 4-64
SRAM Word Address to Physical Address
Mapping 4-26
Status Register (SR) B-14
Stop Delay (SD) bit 3-12
T
T0EN (TCS Transmitter 0 Enable) 6-17
T1EN (TCS Transmitter 1 Enable) 6-17
T2EN (TCS Transmitter 2 Enable) 6-18
TCKP (TCS Transmitter Clock Polarity) 6-19
TCS 6-22
TDIR (TCS Transmitter Data Shift
Direction) 6-18
TDWE (TCS Transmitter Data Word
Expansion) 6-20
Timing Diagrams for DRAM Addressing
Modes 4-51
Timing Diagrams for SRAM Addressing
Modes 4-64
Timing Skew 1-12
TLDE (TCS Transmitter Left Data Empty) 6-22
TMST (TCS Transmitter Master) 6-18
TRDE (TCS Transmitter Right Data Empty) 6-23
TREL (TCS Transmitter Relative Timing) 6-20
TWL0-TWL1 (TCS Transmitter Word Length
Control) 6-18
TX0, TX1 and TX2 (SAI Transmit Data
Registers) 6-23
TXIE (TCS Transmitter Interrupt Enable) 6-21
TXIL (TCS Transmitter Interrupt Location) 6-22
Typical DSP56004/007 System Topology C-3
X
X Data Memory 1-15
Y
Y Data Memory 1-15
MOTOROLA DSP56009 User's Manual
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Index-6