Table 5-3 Shi Noise Reduction Filter Mode; Hdm[5:0])—Bits 8–3 - Motorola DSP56009 User Manual

Serial Host Interface
Serial Host Interface Programming Model
HRS is set, the prescaler is bypassed. When HRS is cleared, the fixed divide-by-eight
prescaler is operational. HRS is ignored when the SHI operates in the Slave mode.
The HRS bit is cleared during hardware reset and software reset.
5.3.5.3 HCKR Divider Modulus Select (HDM[5:0])—Bits 8–3
The HDM[5:0] bits specify the divide ratio of the clock generator divider. A divide
ratio between 1 and 64 (HDM[5:0] = 0 to $3F) may be selected. When the SHI operates
in the Slave mode, the HDM[5:0] bits are ignored. The HDM[5:0] bits are cleared
during hardware reset and software reset.
5.3.5.4 HCKR Reserved Bits—Bits 23–14, 11–9
These bits in HCKR are reserved and unused. They are read as 0s and should be
written with 0s for future compatibility.
5.3.5.5 HCKR Filter Mode (HFM[1:0]) — Bits 13–12
The read/write control bits HFM[1:0] specify the operational mode of the noise
reduction filters as described in Table 5-3 on page 5-12. The filters are designed to
eliminate undesired spikes that might occur on the clock and data-in lines and allow
the SHI to operate in noisy environments when required. One filter is located in the
input path of the SCK/SCL line and the other is located in the input path of the data
line (i.e., the SDA line when in I
and the MOSI line when in SPI Slave mode).
HFM1
0
0
1
1
When HFM[1:0] are cleared, the filter is bypassed (spikes are not filtered out). This
mode is useful when higher bit-rate transfers are required and the SHI operates in a
noise-free environment.
When HFM1 = 1 and HFM0 = 0, the narrow-spike-tolerance filter mode is selected. In
this mode the filters eliminate spikes with durations of up to 20ns. This mode is
suitable for use in mildly noisy environments and imposes some limitations on the
maximum achievable bit-rate transfer.
5-12
2
C mode, the MISO line when in SPI Master mode,

Table 5-3 SHI Noise Reduction Filter Mode

HFM0
0 Bypassed (Disabled)
1 Reserved
0 Narrow Spike Tolerance
1 Wide Spike Tolerance
DSP56009 User's Manual
Description
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