Emi Refresh Clock Divider (Ecd[7:0])—Bits 0–7 - Motorola DSP56009 User Manual

External Memory Interface
EMI Programming Model
4.2.8.1 EMI Refresh Clock Divider (ECD[7:0])—Bits 0–7
The read/write EMI Refresh Clock Divider (ECD[7:0]) bits are used to preset an 8-bit
counter that generates the DRAM refresh requests (if DRAM refresh is enabled). The
counter itself is not accessible to the user. When the counter reaches zero, it is
reloaded from the ECD[7:0] bits. The divide rate range is between 1 (ECD[7:0]= $00)
and 256 (ECD[7:0] = $FF).
Note: The ECD[7:0] bits are cleared by hardware reset and software reset.
4.2.8.2 ERCR Reserved Bits—Bits 8–17, 21
These bits in the ERCR are reserved and unused. They read as 0s and should be
written with 0s for future compatibility.
4.2.8.3 EMI Refresh Clock Prescaler (EPS[1:0])—Bits 18–19
The read/write EMI refresh clock Prescaler (EPS[1:0]) bits control a prescaler that is
connected in series with the refresh clock divider. These bits are used to extend the
range of the refresh clock divider when a slower refresh clock rate is desired. When
EPS[1:0] = 00, a divide-by-64 prescaler is connected in series with the refresh clock
divider. When EPS[1:0] = 01, a divide-by-8 prescaler is connected in series with the
refresh clock divider. When EPS[1:0] = 10, the prescaler is bypassed. EPS[1:0] = 11 is
reserved for future expansion.
Note: The EPS[1:0] bits are cleared by hardware reset and software reset.
4.2.8.4 EMI One-Shot Refresh (EOSR)—Bit 20
The read/write EMI One-Shot Refresh (EOSR) bit is used to trigger one DRAM
refresh cycle under software control. When EOSR is set, one Column Address Strobe
(CAS) before Row Address Strobe (RAS) refresh cycle is generated, independent of
the state of bits EREF and ERED (see below). The EOSR bit is automatically cleared
by the EMI hardware after the refresh cycle has been generated. The refresh cycle will
be generated immediately if no word transfer is occurring, or at the end of the
current word access if a word transfer is in progress.
Note: The EOSR bit is cleared by hardware reset and software reset.
4.2.8.5 EMI Refresh Enable when Debugging (ERED)—Bit 22
The read/write control bit EMI Refresh Enable when Debugging (ERED) is used to
enable DRAM refresh cycles when the DSP enters Debug mode if EREF is cleared.
When ERED is set, CAS before RAS refresh cycles are inserted between data word
transfers while the DSP is in the Debug mode independent of the state of EREF.
Refresh cycle requests are generated according to the output clock rate of the refresh
timer. If ERED is cleared, refresh cycle insertion is disabled when the DSP leaves the
Debug mode.
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