Table 4-9 Emi Read/Write Interrupt Select; Emi Interrupt Select (Eis[1:0])—Bits 9–10 - Motorola DSP56009 User Manual

If EINW is cleared, EBARx will not be modified after write operations. If EINW is set,
the contents of EBARx will be incremented by one after generating the address for
the write operation. This bit affects all operating modes. EINW is cleared by
hardware reset and software reset.
4.2.7.6 EMI Interrupt Select (EIS[1:0])—Bits 9–10
The read/write EMI Interrupt Select (EIS[1:0]) control bits are used to select the
condition that will trigger an EMI read/write interrupt. When EIS[1:0] = 00, EMI read
and write interrupts are disabled. When EIS[1:0] = 01, a write-interrupt vector will be
generated when the EDWR becomes empty (EDWE = 1). When EIS[1:0] = 10, a
read-interrupt vector will be generated when the EDRR becomes full (EDRF = 1).
When EIS[1:0] = 11, a read- interrupt vector will be generated when both the EDRB
and the EDRR are full (EBDF = 1). Table 4-9 summarizes the functionality of the
interrupt select bits.
Note: EIS[1:0] are cleared by hardware reset and software reset.
Note: Clearing EIS[1:0] will mask pending EMI interrupts, but after a
one-instruction-cycle delay. If EIS[1:0] are cleared in a long interrupt service
routine, it is recommended that at least one other instruction should separate
the instruction that clears EIS[1:0] and the RTI instruction at the end of the
interrupt service routine.
EIS1
0
0
1
1
4.2.7.7 EMI Memory-Wrap Interrupt Enable (EMWIE)—Bit 11
The read/write control bit EMI Memory-Wrap Interrupt Enable (EMWIE) enables
interrupts when the relevant EBAR is incremented by one (controlled by EINR and
EINW) and wrapped around from the largest word address in the pre-programmed
memory space. When EMWIE is cleared, memory-wrap interrupts are disabled.
When EMWIE is set, memory-wrap interrupts are enabled with separate interrupt
vectors for each of EBAR0 and EBAR1. The largest word address is reached when the
value of the significant bits in EBARx is all 1s. The number of the significant bits in
EBARx involved with address generation can be concluded from Table 4-13
MOTOROLA

Table 4-9 EMI Read/Write Interrupt Select

EIS0
0 Read and Write Interrupts Disabled
1 Write Interrupt Enabled
0 Read Interrupt Enabled if EDRF = 1
1 Read Interrupt Enabled if EBDF = 1
DSP56009 User's Manual
External Memory Interface
EMI Programming Model
Word Length
4-17