Emi Operating Considerations - Motorola DSP56009 User Manual

External Memory Interface

EMI Operating Considerations

4.5 EMI OPERATING CONSIDERATIONS
This section describes aspects of EMI operation that should be particularly noted by
designers of applications using the EMI.
4.5.1 EMI Triggering and Pipelining
The EMI is double-buffered in both the address and the data paths. This feature
allows for pipelined operation of consecutive read or write accesses. Thus, while a
memory access is being performed, the next access can be triggered, proceed through
to the address calculation stage where it is kept on hold until the current access is
completed. As a result, the EMI performance is increased since the address
calculation overlaps with actual memory access, and while the DSP side is
interrupted for service, the next access is being executed on the memory side.
The EMI accepts three types of triggering: DRAM refresh, write transfer, and read
transfer. The EMI always completes its current operation before checking for
pending triggers. The DRAM refresh has the highest priority. Write and read
transfers have the same priority and are serviced according to the arrival order.
When the EMI is idle, two consecutive operations can be triggered without the need
to check status bits for any combination of read and write triggers. As long as a
trigger is pending, any additional trigger will override and replace the pending one.
For better reference to the DSP core activity, EMI data accesses can be measured in
instruction cycles (I
access durations are denoted by "N" I
on page 4-19 and Table 4-11 on page 4-20 by dividing the number of clock cycles by
2. For cases where the number of clock cycles is odd, N can be rounded up
(conservative approach), or for consecutive EMI accesses N can be rounded
alternately up and down.
The EMI pipeline mechanism operates according to the following rules:
• If both read and write data paths are free (EBSY = 0 and EBDF = 0), and a
trigger is generated, it is considered as the first trigger. When this occurs:
– EBSY is set immediately,
– the address calculation is executed at the next I
– the external access starts at the next cycle after I
4-38
) where one I equals two processor clock cycles. EMI data
cyc cyc
cyc
DSP56009 User's Manual
. N can easily be obtained from Table 4-10
cyc
cyc
, and
and ends N I later.
cyc
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