Dram Absolute Addressing - Motorola DSP56009 User Manual

External Memory Interface
EMI Address Generation
4.3.4

DRAM Absolute Addressing

The DRAM Absolute Addressing mode is selected when EAM[3:0] = 11xx. In this
addressing mode, no extension bits are used in the physical address generation.
• EAM[3:0] = '1100'—The physical address is formed by multiplexing the
sixteen LSBs of the calculated word address (A[15:0]) into the MA[7:0] address
pins. The row address is formed by the least significant part (A[7:0]) and the
column address is formed by the remaining bits of the word address (A[15:8]).
• EAM[3:0] = '1101'—The physical address is formed by multiplexing the
eighteen LSBs of the calculated word address (A[17:0]) into the MA[8:0]
address pins. The row address is formed by the least significant part (A[8:0])
and the column address is formed by the remaining bits of the word address
(A[17:9]).
• EAM[3:0] = '1110'—The physical address is formed by multiplexing the
twenty LSBs of the calculated word address (A[19:0]) into the MA[9:0] address
pins. The row address is formed by the least significant part (A[9:0]) and the
column address is formed by the remaining bits of the word address
(A[19:10]).
• EAM[3:0] = '1111'—The physical address is formed by multiplexing the
twenty-two LSBs of the calculated word address (A[21:0]) into the
MA[10:0]address pins. The row address is formed by the least significant part
(A[10:0]) and the column address is formed by the remaining bits of the word
address (A[21:11]).
If more than one physical address must be accessed to complete the word transfer,
EBARx must be post-incremented by one after each physical address access,
otherwise the same physical address will be accessed more than once. To prevent this
occurrence, the appropriate ECSR control bit should be set (EINR for reads, EINW for
writes). The EMI will execute the series of accesses required, incrementing EBARx
after each access, packing (during a read operation) or unpacking (during a write
operation) the data word segments. The accesses proceed from the least significant to
the most significant portion of the word. For each of the accesses, the contents of
EBARx and EOR/EWOR are written to the ALU. The contents of the relevant EBARx
and EOR/EWOR should not be changed during the word transfers.
In the DRAM Absolute Addressing mode, each physical address access is executed
as an independent "out-of-page" DRAM access. As a result, a data word transfer
when executed in the DRAM Absolute Addressing mode is slower than a transfer
executed in the DRAM Relative Addressing mode (see Table 4-10 on page 4-19). The
DRAM Absolute Addressing modes, however, are useful when 20- or 24-bit data
words are used and the wasted memory locations that appear in the DRAM Relative
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