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4.2.7.15
EMI Enable (EME)—Bit 23
The read/write control bit EMI Enable (EME) enables the EMI for data-transfer
operations. When EME is set, the EMI accepts data transfer triggers and executes
data transfers. When EME is cleared, the EMI enters the individual reset state, that is,
the EMI is disabled for data transfers and the status flags in the ECSR are reset to the
same states as during hardware reset. When EME is cleared, the EMI pins are reset to
the state defined in Section 2: Pin Descriptions but the control bits are unaffected.
The individual reset state is entered one instruction cycle after clearing EME. DRAM
refresh operation, if previously enabled, will continue while the EMI is in the
individual reset state.
Note: EME is cleared by hardware reset and software reset.
4.2.8
EMI Refresh Control Register (ERCR)
The EMI Refresh Control Register (ERCR) is a 24-bit read/write register used to
control the refresh of DRAM memories. Refresh can only occur while the EMI is set
to work with DRAM memories (EAM[3:0] = x1xx) or while in the SRAM Absolute
Addressing mode (EAM[3:0] = 0000). The ERCR is cleared by hardware reset and
software reset. The ERCR bits are shown in Figure 4-3 and are described in the
following paragraphs.
11
10
9
8
23
22
21
20
EREF ERED
EOSR
Reserved Bit
Figure 4-3 EMI Refresh Control Register (ERCR)
MOTOROLA
7
6
5
4
ECD7
ECD6
ECD5
ECD4
19
18
17
16
EPS1
EPS0
DSP56009 User's Manual
External Memory Interface
EMI Programming Model
3
2
1
0
ECD3
ECD2
ECD1
ECD0
15
14
13
12
Refresh Rate
Prescaler Rate
One-Shot Refresh
Refresh Enable(Debug)
Refresh Enable
AA0295
4-21
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