Figure 4-4 Emi Address Generation Block Diagram; Ercr Refresh Enable (Eref)—Bit 23 - Motorola DSP56009 User Manual

Note: The ERED bit is cleared by hardware reset and software reset.
4.2.8.6 ERCR Refresh Enable (EREF)—Bit 23
The read/write control bit EREF is used to enable DRAM refresh cycles. When set,
CAS before RAS refresh cycles are inserted between data word transfers for both
regular DSP operation and if the DSP is in the Debug mode. Refresh cycle requests
are generated according to the output clock rate of the refresh timer. If EREF is
cleared, refresh cycle insertion is disabled.
Note: The EREF bit is cleared by hardware reset and software reset.
4.3 EMI ADDRESS GENERATION
Address generation for external memory accesses is done by the EMI in the Address
Generation Unit (AGU). A block diagram of the AGU is shown in Figure 4-4. The
AGU forms a word address for a read operation by subtracting the contents of the
EOR from the contents of the appropriate EBAR. For a write operation, the word
address is formed by subtracting the contents of the EWOR from the contents of the
appropriate EBAR. The word address must then be transformed into one or more
physical addresses as required for loading/storing the data word. The mapping from
word address to physical addresses is described in the following sections. The Base
Address Register in use can be optionally incremented by one after calculating the
word address.
+1 Base Address
Word Address: A23–A0

Figure 4-4 EMI Address Generation Block Diagram

MOTOROLA
24
ALU
24
Address Format
Conversion
EMI Address and Chip Select Pins
DSP56009 User's Manual
External Memory Interface
EMI Address Generation
Offset Register
24
C2–C0
3
Relative Addressing
Extension Bits
AA0296
4-23