Multiplier-Accumulator (Mac); Address Generation Unit (Agu) - Motorola DSP56305 User Manual

DSP56305 Overview
DSP56300 Core Functional Blocks
All the Data ALU operations are performed in two clock cycles in pipeline fashion so
that a new instruction can be initiated in every clock, yielding an effective execution rate
of one instruction per clock cycle. The destination of every arithmetic operation can be
used as a source operand for the immediately following arithmetic operation without a
time penalty (i.e., without a pipeline stall).
1.6.1.2

Multiplier-Accumulator (MAC)

The Multiplier-Accumulator (MAC) unit comprises the main arithmetic processing unit
of the DSP56300 core and performs all of the calculations on data operands. In the case of
arithmetic instructions, the unit accepts as many as three input operands and outputs
one 56-bit result of the following form, Extension:Most Significant Product:Least
Significant Product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between
two's-complement signed, unsigned, or mixed operands. The 48-bit product is
right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit
result can be stored as a 24-bit operand. The LSP can either be truncated or rounded into
the MSP. Rounding is performed if specified.
1.6.2

Address Generation Unit (AGU)

The AGU performs the effective address calculations using integer arithmetic necessary
to address data operands in memory and contains the registers used to generate the
addresses. It implements four types of arithmetic: linear, modulo, multiple wrap-around
modulo, and reverse-carry. The AGU operates in parallel with other chip resources to
minimize address-generation overhead.
The AGU is divided into two halves, each with its own Address Arithmetic Logic Unit
(Address ALU). Each Address ALU has four sets of register triplets, and each register
triplet is composed of an address register, an offset register, and a modifier register. The
two Address ALUs are identical. Each contains a 16-bit full adder (called an offset
adder).
A second full adder (called a modulo adder) adds the summed result of the first full
adder to a modulo value that is stored in its respective modifier register. A third full
adder (called a reverse-carry adder) is also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs.
The only difference between them is that the carry propagates in opposite directions.
Test logic determines which of the three summed results of the full adders is output.
MOTOROLA DSP56305 User's Manual 1-9