Select Bit C (Sbc[4:0])—Csfs Bits 20–16; Select Register C (Src[1:0])—Csfs Bits 22–21; Reserved Bits—Csfs Bits 7, 15, 23; Step Function Table A (Csfta) - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
14.4.3.1.5 Select Bit C (SBC[4:0])—CSFS Bits 20–16
The Select Bit C (SBC[4:0]) bits determine which bit (0 to 23) in a particular CFSR is
selected as the last (MSB) address line of the Step Function Table. Which CFSR is used is
determined by bits SRC[1:0] in CSFS. The values 24 to 31 are invalid and should not be
used.
14.4.3.1.6 Select Register C (SRC[1:0])—CSFS Bits 22–21
The Select Register C (SRC[1:0]) bits select which CFSR from which the selected bit (by
SBC[4:0]) is connected to the last (MSB) address line of the Step Function Table. The
combination of SBC[4:0] and SRC[1:0] determine which bit of which CFSR is used as the
last address line of the Step Function Table.
14.4.3.1.7 Reserved Bits—CSFS Bits 7, 15, 23
These bits are reserved and should be written as zero for future compatibility.
14.4.3.2

Step Function Table A (CSFTA)

The Step Function Table A (CSFTA) is a 24-bit read/write register containing the first six
words of the Step Function Table. The words are 4-bit width.
11 10 9
WRDC3 WRDC2 WRDC1 WRDC0 WRDB3 WRDB2 WRDB1 WRDB0 WRDA3 WRDA2 WRDA1 WRDA0
23 22 21
WRDF3 WRDF2 WRDF1

Figure 14-6 Step Function Table A Register (CSFTA)

14.4.3.3

Step Function Table B (CSFTB)

The Step Function Table B (CSFTB) is a 24-bit read/write register containing the last two
4-bit words of the Step Function Table. In addition, CSFTB is used to enable the data
input into the CFSRs during the input phase (using INE[3:0], CSFTB Bits 19–16), and to
enable the data output data from the CFSRs during the output phase (using OUT[3:0],
CSFTB Bits 23–20).
14-12
8 7 6
20 19 18
WRDF0 WRDE3 WRDE2 WRDE1 WRDE0 WRDD3 WRDD2 WRDD1 WRDD0
DSP56305 User's Manual
5 4 3
17 16 15
2 1 0
14 13 12
AA1305
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