Timer Toggle (Mode 2) - Motorola DSP56305 User Manual

9.4.1.3

Timer Toggle (Mode 2)

Bit Settings
TC3 TC2 TC1
0 0 1
In this mode, the timer periodically toggles the polarity of the TIO signal.
Set the TE bit (TCSR Bit 0) to clear the counter and enable the timer. Load the timer count
value into the TCPR. The counter is loaded with the TLR value when the first timer clock
signal is received. The TIO signal is loaded with the value of the INV bit (TCSR Bit 8).
The timer clock signal can be taken from either the DSP56300 clock divided by two
(CLK/2) or from the prescaler clock output. Each subsequent timer clock signal
increments the counter.
When the counter value matches the TCPR value, the polarity of the TIO output signal is
inverted. The TCF bit (TCSR Bit 21) is set and, if the TIE bit (TCSR Bit 2) is set, a compare
interrupt is generated. On the next timer clock signal, if the TRM bit (TCSR Bit 9) is set,
the counter is loaded with the TLR value and the count is resumed; but if the TRM bit is
cleared, the counter continues to be incremented on each timer clock signal.
This process is repeated until the timer is disabled (i.e., until the TE bit is cleared). If the
counter overflows, the TOF bit (TCSR Bit 20) is set, and if the TOIE bit (TCSR Bit 1) is set,
an overflow interrupt is generated. The counter contents can be read at any time by
reading the TCR.
The TLR value and the TCPR sets the delay between starting the timer and toggling the
TIO signal. To generate output signals with a delay of X clock cycles between toggles
(assuming a clock of CLK/2), the TLR value should be set to 0, the TCPR should be set to
X/2, and the TRM bit should be set.
Note: The TIO bit polarity is dependent on the INV bit value. When TE is set, the
TIO signal output value is put equal to the INV bit value to guarantee the first
signal transition is correct.
MOTOROLA
TC0 TIO Clock
0 Output Internal
DSP56305 User's Manual
Timer Modes of Operation
Mode Characteristics
# KIND
0 Timer
Timer/Event Counter
NAME
Toggle
9-21