Parity Coding Modes; Parity Coding Mode Using One Cfsr; Using Two Concatenated Cfsrs - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR
Operating Modes
the user to change CFSR configuration after each step. Every step is activated by setting
PREN, and is halted automatically after completing a single shift of the session by
clearing PREN and entering the Idle state. A single step session in the Step-by-step
Cipher mode takes two DSP clocks to complete, therefore for proper operation, a step
can be re-activated (PREN = 1) every two or more DSP clock cycles.
14.5.2

Parity Coding Modes

When OPM1 is set, the CCOP operates in one of the Parity Coding modes. In these
modes the CFSRs are configured as shown in Figure 14-3 CFSR Configuration in the
Parity Coding Modes on page 14-6. The Parity Coding modes are used to calculate a
Cyclic Redundancy Code (CRC) syndrome for encoding or decoding. When in the Parity
Coding modes:
• The Feedback Tap register (CFBT) specifies the position of the taps between
adjacent bits of the CFSR connected to the feedback line.
• The Feedforward Tap register (CFFT) specifies the position of the taps of the
pre-multiplier polynomial.
• The Bit Select register (CBSR) specifies which bits from the CFSR are selected for
use by the Zero Detect function.
• The Mask register (CMSK) selects the bit in the CFSR which drives the feedback
line. In both Parity Coding modes, the bit driving the feedback line is always
selected by programming Mask Register A (CMSKA).
In the Parity Coding modes, the Mask tap register (i.e. CMSKA) should have only one bit
set, specifying the CFSR (CFSRA) bit by which the feedback is driven (i.e. the degree of
the generator polynomial). In the Parity Coding modes the bitwise majority function and
the output phase are disabled. The Zero Detect function is enabled (if HOZD, CCSR Bit
9, is set) and can affect the processing. Therefore, the relevant output data are the
contents of the CFSRs, and in some cases the counter values.
14.5.2.1

Parity Coding Mode Using One CFSR

When OPM[1:0] = 10 only the first CFSR (CFSRA) is enabled. In this mode, cyclic parity
codes using generator polynomials of up to 24 stages (maximum degree of 24) can be
generated.
14.5.2.2 Parity Coding Mode Using Two Concatenated CFSRs
When OPM[1:0] = 11 only two CFSRs (CFSRA and CFSRB) are enabled and
concatenated together to form one double-length CFSR. CFSRB and CFSRA are
positioned on the left and right sides respectively, while the LSB of CFSRB drives the
MSB of CFSRA. In this mode, cyclic parity codes using generator polynomials of up to 48
14-22 DSP56305 User's Manual MOTOROLA