Motorola DSP56305 User Manual page 336

Serial Communication Interface (SCI)
SCI Programming Model
STXL, STXM or STXH is written. When either STX (STXL, STXM, or STXH) or STXA is
written, TDRE is cleared.
The transfer from either STX or STXA to the Transmit Shift Register occurs
automatically, but not immediately, when the last bit from the previous word has been
shifted out; that is, when the Transmit Shift Register is empty. Like the receiver, the
transmitter is double-buffered. However, a 2 to 4 serial clock cycle delay occurs between
when the data is transferred from either STX or STXA to the Transmit Shift Register and
when the first bit appears on the TXD signal. (A serial clock cycle is the time required to
transmit one data bit). The Transmit Shift Register is not directly addressable, and a
dedicated flag for this register does not exist. Because of this fact and the 2 to 4 cycle
delay, two bytes cannot be written consecutively to STX or STXA without polling, as the
second byte might overwrite the first byte. The TDRE flag should always be polled prior
to writing STX or STXA to prevent overruns unless transmit interrupts have been
enabled. Either STX or STXA is usually written as part of the interrupt service routine.
An interrupt is generated only if TDRE is set. The Transmit Shift Register is indirectly
visible via the TRNE bit in the SSR.
In the Synchronous mode, data is synchronized with the transmit clock, which can have
either an internal or external source, as defined by the TCM bit in the SCCR. The length
and format of the serial word is defined by the WDS0, WDS1, and WDS2 control bits in
the SCR. In the Asynchronous modes, the start bit, the eight data bits (with the LSB first
if SSFTD = 0 and the MSB first if SSFTD = 1), the address/data indicator bit or parity bit,
and the stop bit are transmitted in that order.
The data to be transmitted can be written to any one of the three STX addresses. If SCKP
is set and SSHTD is set, the SCI Synchronous mode is equivalent to the SSI operation in
the 8-bit Data On-demand mode.
Note: When writing data to a peripheral device there is a two cycle pipeline delay
until any status bits affected by this operation are updated. If the user reads
any of those status bits within the next two cycles, the bit will not reflect its
current status. See the DSP56300 Family Manual, Appendix B, "Polling a
Peripheral Device for Write," for further details.
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