Input Enable Bits (Ine[3:0])—Csftb Bits 19–16; Figure 14-7 Step Function Table B Register (Csftb); Table 14-2 Step Function Table - Motorola DSP56305 User Manual

11 10 9
23 22 21
OUTE3 OUTE2 OUTE1 OUTE0 INE3
Reserved bit, Read as zero, should be written with zero for future compatibility

Figure 14-7 Step Function Table B Register (CSFTB)

Together, CSFTA and CSFTB form the Step Function Table as shown in Table .
14.4.3.4 Input Enable bits (INE[3:0])—CSFTB Bits 19–16
The Input Enable bits (INE[3:0]) are used to enable data input into CFS[D:A] respectively
during the input phase. When the INEx bit is cleared, data input to CFSRz is disabled for
the input phase. When the INEx bit is set, data input to CFSRz is enabled for the input
phase. Table 14-3 lists the bit numbers and their corresponding registers.
MOTOROLA
8 7
WRDH3 WRDH2 WRDH1 WRDH0WRDG3WRDG2WRDG1WRDG0
20 19 18
INE2

Table 14-2 Step Function Table

Word
Data Bits
Address
0 WRDA[3:0]
1 WRDB[3:0]
2 WRDC[3:0]
3 WRDD[3:0]
4 WRDE[3:0]
5 WRDF[3:0]
6 WRDG[3:0]
7 WRDH[3:0]
DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
6 5 4
17 16
INE1 INE0
Bit Location
CSFTA 3–0
CSFTA 7–4
CSFTA 11–8
CSFTA 15–12
CSFTA 19–16
CSFTA 23–20
CSFTB 3–0
CSFTB 7–4
CCOP Programming Model
3 2 1
15 14 13
0
12
AA1306
14-13