Table 14-7 Operations During Cipher Mode Processing; Cipher Mode Initialization; Cipher Mode Output - Motorola DSP56305 User Manual

Table summarizes the operations being conducted at the input, run and output phases
in every (enabled) CFSR during a Cipher processing session.

Table 14-7 Operations During Cipher Mode Processing

Input Data
Shifts
Output Data
14.6.4.1

Cipher Mode Initialization

Assuming the CCOP is in the CCOP individual reset state, a Cipher processing session is
initialized by the following steps. There is no required order to these steps except that
data should be written to the CFSRs and CDFR while CCOP is enabled (CEN in CCSR is
set), and the counter and configuration registers (CCNT, CSFS, CSFTA, and CSFTB)
should be written when the processing is disabled (PREN in CCSR is cleared).
1. Enable CCOP in Cipher mode (in CCSR: set CEN, clear PREN, clear OPM1, and
program OPM0 and LRC as required).
2. Initialize CFSRs value as required (CFSRA, CFSRB, CFSRC, and CFSRD).
3. Configure CFSRz parameter registers as required by the Cipher algorithm
(CFBTz, CFFTz, CBSRz, and CMSKz).
4. Initialize the counter register (CCNT), step function select register (CSFS) and
step function table and input/output enable registers (CSFTA and CSFTB).
5. Write the input data block into the Data FIFO Register (CDFR).
6. Enable processing (set PREN in CCSR).
14.6.4.2

Cipher Mode Output

After Cipher processing is completed (i.e., CIDN is set), the DSP56300 core should read
the output data sequence from the Data FIFO Register (CDFR). CIDN is cleared after all
expected data words were read from CDFR.
MOTOROLA
Input Phase
Enabled if INEx
in CSFTB set
Enabled Enabled according to
Step Function Table
Disabled
DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
Programming Considerations
Run Phase
Disabled
Enabled according to
Step Function Table
Disabled Enabled if OUTEx
Output Phase
Disabled
in CSFTB set
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