Timer Control/Status Register (Tcsr); Figure 9-6 Timer Programming Model - Motorola DSP56305 User Manual

Timer/Event Counter
Timer Architecture
7 6
TC3 TC2
15 14
PCE
23 22
23
23
23
- reserved, read as 0, should be written with 0 for future compatibility
9.3.3

Timer Control/Status Register (TCSR)

The Timer Control/Status Register (TCSR) is a 24-bit read/write register controlling the
timer and reflecting its status. The control and status bits are described below.
9-10
5 4 3 2
TC1 TC0 TCIE
13 12 11 10
DO DI DIR
21 20 19 18
TCF TOF

Figure 9-6 Timer Programming Model

DSP56305 User's Manual
1 0
TOIE TE
Timer Control/Status
Register (TCSR)
9 8
TCSR0 = $FFFF8F
TCSR1 = $FFFF8B
TRM
INV
TCSR2 = $FFFF87
17 16
0
Timer Load
Register (TLR)
TLR0 = $FFFF8E
TLR1 = $FFFF8B
TLR2 = $FFFF87
0
Timer Compare
Register (TCPR)
TCPR0 = $FFFF8F
TCPR1 = $FFFF86
TCPR2 = $FFFF87
0
Timer Count
Register (TCR)
TCR0 = $FFFF8C
TCR1 = $FFFF88
TCR2 = $FFFF84
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