Table 6-12 Hi32 Pci Target Execution - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
HC3/HBE3-HC0/HBE0
a. All internal address decoding is ignored and DEVSEL is not asserted.
The master data transfer format control bits (FC1-FC0 in the DPMC) affect the
HTXR-DRXR and DTXM-HRXM data paths only. The target data transfer format control
bits (HTF1-HTF0 and HRF1-HRF0 in the HCTR) affect the HTXR-DRXR and
DTXS-HRXS data paths only. The data paths to the other host registers (HCTR, HSTR,
HCVR, CDID/CVID, CSTR/CCMR, CCCR/CRID, CHTY/CLAT, CBMA and CILP) are
not affected by the data transfer format control bits.
The host side registers can be accessed by the host processor. The CCMR, CLAT and
CBMA HI32 configuration registers can also be accessed, indirectly, by the DSP56300
core in the Self Configuration mode (HM = $5 - see Section 6.5.1.13).
Reserved addresses are read as zeros, and should be written with zeroes for future
compatibility.
6-50

Table 6-12 HI32 PCI Target Execution

0000
ignored
0001
ignored
0010
ignored
0011
ignored
0100
ignored
0101
ignored
0110 Memory Read
0111 Memory Write
1000
ignored
1001
ignored
1010 Configuration Read
1011 Configuration Write
1100 Memory Read
1101
ignored
1110 Memory Read
1111 Memory Write
DSP56305 User's Manual
Executed as Command Type
a
(a)
(a)
(a)
(a)
(a)
(a)
(a)
(a)
MOTOROLA