Force Shift Bit (Fosh)—Ccsr Bit 10; Data In Interrupt Enable Bit (Diie)—Ccsr Bit 12; Data Out Interrupt Enable Bit (Doie)—Ccsr Bit 13 - Motorola DSP56305 User Manual

• the bits specified by the Bit Select registers CBSRA or CBSRB in Parity Coding
Mode using two concatenated CFSRs (OPM[1:0] = 11)
In this case the processing is terminated (PREN is cleared and PCDN is set) and the Run
Counter can be used to calculate the pointer to the erroneous burst in the data sequence
that should be corrected.
14.4.4.6 Force Shift bit (FOSH)—CCSR Bit 10
The FOrce SHift bit (FOSH) is a control bit used to force an unconditional extra shift in
all CFSRs during a Cipher processing session. FOSH is operational in the Step-by-step
Cipher mode only (OPM[1:0] = 01), and is ignored otherwise. When FOSH is cleared and
a new step is activated (PREN is set), a single shift is executed to CFSRs selected
according to the Step Function Table (if this step belongs to the run or output phase), the
associated counter is decremented (which counter is decremented depends on which
processing phase this particular step belongs to), and an output bit is generated (if this
step belongs to the output phase). After this single step is accomplished PREN is
automatically cleared causing CCOP to re-enter the Idle state. When FOSH is set and a
new step is activated (PREN is set) a single shift is forced to all CFSRs independent of the
Step Function Table. This extra shift can be inserted at any Cipher processing operating
phase. It does not cause any counter decrement and (if executed in the output phase)
does not generate an output bit to the output FIFO. Combining doing a single step with
FOSH cleared and a single step with FOSH set accomplishes one step of the Cipher
process in which the stepping function varies between 1 and 2 shifts instead of 0 and 1
shift.
14.4.4.7 Data In Interrupt Enable bit (DIIE)—CCSR Bit 12
The Data In Interrupt Enable bit (DIIE), when set, enables the interrupt caused by the
input FIFO empty signal (when the INFE bit, CCSR Bit 20, is set). When INFE is cleared,
the interrupt is disabled.
14.4.4.8 Data Out Interrupt Enable bit (DOIE)—CCSR Bit 13
The Data Out Interrupt Enable bit (DOIE), when set, enables the interrupt caused by the
output FIFO not empty signal (when the OFNE bit, CCSR Bit 21, is set). When OFNE is
cleared, the interrupt is disabled.
14.4.4.9 Cipher Done Interrupt Enable bit (CDIE)—CCSR Bit 14
The Cipher Done Interrupt Enable bit (CDIE), when set, enables the interrupt caused by
terminating CCOP Cipher mode processing (when CIDN, CCSR Bit 22, is set). If both
CDIE and CIDN bits are set, the CCOP requests a Cipher Done interrupt request from
the interrupt controller. When CDIE is cleared, the interrupt is disabled.
14.4.4.10 Parity Coding Done Interrupt Enable bit (PDIE)—CCSR Bit 15
The Parity Coding Done Interrupt Enable bit (PDIE), when set, enables the interrupt
caused by terminating the CCOP Parity Coding mode processing (when PCDN, CCSR
MOTOROLA DSP56305 User's Manual
CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
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