Motorola DSP56305 User Manual page 659

mode 0—GPIO 9-19
mode 1—timer pulse 9-20
mode 2—timer toggle 9-21
mode 3—timer event counter 9-22
mode 4—measurement input width 9-23
mode 5—measurement input period 9-24
mode 6—measurement capture 9-25
mode 7—pulse width modulation 9-26
mode 8—reserved 9-27
mode 9—watchdog pulse 9-27
mode 10—measurement toggle 9-28
modes 11–15—reserved 9-29
Timer module
architecture 9-3
timer block diagram 9-3
Timer Overflow Flag bit (TOF) 9-16
Timer Overflow Interrupt Enable bit (TOIE) 9-11
Timer Prescaler Count Register (TPCR) 9-7
Timer Prescaler Load Register (TPLR) 9-5
Timer Reload Mode bit (TRM) 9-14
Timer/Event Counter 1-17
Timer/Event Counter module 1-17
, ,
Timers 2-3 2-4 2-37
TLIE bit 7-34
TLR register 9-17
TME bit 10-8
TMIE bit 8-13
TMS pin 11-5
TO bit 10-9
TOF bit 9-16
TOIE bit 9-11
TPCR register 9-7
bits 0-20—Prescaler Counter Value bits
(PC0-PC20) 9-7
bit 21-23—reserved bits 9-7
reserved bits—bits 21-23 9-7
TPLR register 9-5
bits 0-20—Prescaler Load Value bits
(PL0-PL20) 9-6
bits 21-22—Prescaler Source bits
(PL0-PL20) 9-6
bit 23—reserved bit 9-6
reserved bit—bit 23 9-6
Trace buffer 10-21
Trace mode
enabling 10-18
in OnCE module 10-15
Trace Mode Enable bit (TME) 10-8
Trace Occurrence bit (TO) 10-9
Transmit 0 Enable bit (TE0) 7-31
Transmit 1 Enable bit (TE1) 7-30
MOTOROLA
Transmit 2 Enable bit (TE2) 7-29
Transmit Clock Source bit (TCM) 8-20
Transmit Data Register Empty bit (TDE) 7-37
Transmit Data Register Empty bit (TDRE) 8-14
Transmit Data signal (TXD) 8-4
Transmit Exception Interrupt Enable bit
Transmit Frame Sync Flag bit (TFS) 7-36
Transmit Interrupt Enable bit (TIE) 7-34
Transmit Last Slot Interrupt Enable bit (TLIE) 7-34
Transmit Shift Registers 7-40
Transmit Slot Mask Registers (TSMA, TSMB) 7-41
Transmitter Empty bit (TRNE) 8-14
Transmitter Enable bit (TE) 8-12
Transmitter Underrun Error Flag bit (TUE) 7-37
triple timer module 1-17
TRM bit 9-14
TRNE bit 8-14
TRST pin 11-5
TSMA, TSMB registers 7-41
TSR register 7-41
TUE bit 7-37
TX2, TX1, TX0 registers 7-41
TXD signal 8-4
V
VBA register 1-11
Vector Base Address register (VBA) 1-11
W
wait
WAKE bit 8-10
Wakeup Mode Select bit (WAKE) 8-10
WDS0-WDS2 bits 8-9
Wired-OR Select bit (WOMS) 8-11
WL0–WL1 bits 7-19
WOMS bit 8-11
Word Length Control bits (WL0–WL1) 7-19
Word Select bits (WDS0-WDS2) 8-9
X
X data RAM 3-5
X Memory Address Bus (XAB) 1-13
X Memory Data Bus (XDB) 1-13
X Memory Expansion Bus 1-13
XAB 1-13
XDB 1-13
DSP56305 User's Manual
(TEIE) 7-35
standby mode 1-7
V
,
8-13
Index-9