Table 13-1 Vcop Programming Model - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR
Programming Model
13.5 PROGRAMMING MODEL
The VCOP control and status registers are accessible to the DSP56300 core through the
PMB. They are summarized in Table 13-1.
Base
Address
$0
$1
$2
$3
$4
$5
$6
$7
$8
$9
$A
$B
$C
All VCOP registers are 16-bits wide, except VMEM which is 24-bits wide. Data register
(VDR, VDOR, VWED) access to a 24-bit resource (such as a bus, register, memory, etc.) is
left aligned. That is, the 24-bit resource is read as zero padded ($DDDD00) and the data
is written with the eight LSBs ignored ($DDDDXX). Control register (VCRA, VCRB,
VSTR, VCNT, VTPA, VTPB, VTSR, VBER, VWES) access to a 24-bit resource is right
aligned. That is. the registers are read zero padded ($00DDDD) and written with the
eight MSBs ignored ($XXDDDD). When writing the control registers from a 24-bit
resource, the 8 MSBs must be written with 0 for future compatibility.
13-16

Table 13-1 VCOP Programming Model

Register Name
VCOP Data Register/FIFO
VCOP Data Out Register
VCOP Control Register A
VCOP Control Register B
VCOP Status Register
VCOP Data Count Register
VCOP Tap Register A
VCOP Tap Register B
VCOP Trellis Setup Register
VCOP Bit Error Rate Register
VCOP WED Setup Register
VCOP WED Data Register
VCOP Memory Access Register
DSP56305 User's Manual
Register
Abbreviation
VDR
VDOR
VCRA
VCRB
VSTR
VCNT
VTPA
VTPB
VTSR
VBER
VWES
VWED
VMEM
MOTOROLA