Prescaler Counter; Timer Prescaler Load Register (Tplr); Figure 9-2 Timer/Event Counter Programming Model; Figure 9-3 Timer Prescaler Load Register (Tplr) - Motorola DSP56305 User Manual

23
23

Figure 9-2 Timer/Event Counter Programming Model

9.2.3

Prescaler Counter

The prescaler counter is a 21-bit counter decremented on the rising edge of the prescaler
input clock. The counter is enabled when at least one timer is both enabled (i.e., one or
more of the Timer Enable (TE, TCSR Bit 0) bits are set) and using the prescaler output as
its source (i.e., one or more of the Prescaler Clock Enable (PCE, TCSR Bit 15) bits are set).
9.2.4

Timer Prescaler Load Register (TPLR)

The Timer Prescaler Load Register (TPLR) is a 24-bit read/write register that controls the
prescaler divide factor (i. e., the number that the prescaler counter loads and begins
counting from) and the source for the prescaler input clock. The control bits are
described below (see Figure ).
23 22 21
PS1 PS0
11 10 9
PL11 PL10 PL9
— reserved, read as 0, should be written with 0 for future compatibility

Figure 9-3 Timer Prescaler Load Register (TPLR)

MOTOROLA
20 19 18
PL20 PL19 PL18
8 7 6
PL8 PL7 PL6
DSP56305 User's Manual
Timer/Event Counter Architecture
0
Timer Prescaler Load
Register (TPLR)
TPLR = $FFFF83
0
Timer Prescaler Count
Register (TPCR)
TPLR = $FFFF82
17 16 15
PL17 PL16 PL15
5 4 3
PL5 PL4 PL3
Timer/Event Counter
14 13 12
PL14 PL13 PL12
2 1 0
PL2 PL1 PL0
9-5