Motorola DSP56305 User Manual page 646

PROGRAMMING REFERENCE
HI32 Registers - Quick Reference (Sheet 4 of 8)
Reg Bit #
Mnemonic Name
DPSR MWS
MTRQ
MRRQ
MARQ
APER
DPER
MAB
TAB
TDIS
TRTY
TO
HDTC
21-16 RDC5-RDC
0
D-46
PCI Master Wait States
PCI Master Transmit Data
Req.
PCI Master
Receive Data Req.
PCI Master Address Request 1
PCI Address Parity Error
PCI Data Parity Error
PCI Master Abort
PCI Target Abort
PCI Target Disconnect
PCI Target Retry
PCI Time Out Termination
PCI Host Data Transfer
Complete
Remaining Data Count
DSP56305 User's Manual
Val Function
0 HI32 is asserting HIRDY
1 HI32 is negating HIRDY
1 master transmit FIFO is not full
0 master transmit FIFO is full
0 master receive FIFO is empty
1 master receive FIFO is not
empty
core may initiate new
transaction
0 core may not initiate new
transaction
0 HI32 target has not detected an
address parity error
1 HI32 target has detected an
address parity error
0 a data parity error has not
1 occurred
a data parity error has occurred
0 a master abort has not
1 occurred
a master abort has occurred
0 a target abort has not occurred
1 a target abort has occurred
0 a target disconnect has not
1 occurred
a target disconnect has
occurred
0 a target retry has not occurred
1 a target retry has occurred
0 a time-out termination has not
occurred
1 a time-out termination has
occurred
0 HI32 is transferring data to the
core
1 HI32 has completed transfer of
data to the core, and will
disconnect write accesses to
the HTXR
Comments Reset Type
HS PH
0 -
cleared if the (a) -
1
DTXM is filled
by core writes
cleared if the 0 -
DRXR is
emptied by
core reads; or
the data to be
read from the
DRXR is
slave data.
0 0
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
cleared by 0 -
writing 1
may be
written 1 only
if HDTC = 1
- -
MOTOROLA
PS
0
(a)
1
0
0
-
-
-
-
-
-
-
0
-