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Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
7.4.2
ESSI Control Register B (CRB)
The CRB is one of two 24-bit read/write control registers used to direct the operation of
the ESSI (see Figure 7-7). CRB controls the ESSI multifunction signals, SC[2:0], which can
be used as clock inputs or outputs, frame synchronization signals, transmit data signals,
or serial I/O flag signals.
The serial output flag control bits and the direction control bits for the serial control
signals are in the ESSI CRB. Interrupt enable bits for the receiver and the transmitter are
also in the CRB. The bit setting of the CRB also determines how many transmitters are
enabled (0, 1, 2, or 3 transmitters can be enabled). The CRB settings also determine the
ESSI operating mode.
Either a hardware reset signal or a software reset instruction clear all the bits in the CRB.
The relationship between the ESSI signals SC[2:0], SCK, and the CRB bits is summarized
in Table 7-4. See also Figure 7-3, Figure 7-4, Figure 7-5, and Figure 7-15. The ESSI CRB
bits are described in the following paragraphs.
7.4.2.1
Serial Output Flags (OF[1:0]) CRB Bits 1-0
The ESSI has two serial output flag bits, OF1 and OF0. The normal sequence for setting
output flags when transmitting data (by transmitter 0 through the STD signal only) is:
1. Wait for TDE (TX0 empty) to be set.
2. Write the flags.
3. Write the transmit data to the TX register.
Bits OF0 and OF1 are double-buffered so that the flag states appear on the signals when
the TX data is transferred to the Transmit Shift Register. The flag bits values are
synchronized with the data transfer.
Note:
The timing of the optional serial output signals SC[2:0] is controlled by the
frame timing and is not affected by the settings of TE2, TE1, TE0, or the
Receive Enable (RE) bit of the CRB.
7.4.2.1.1
Serial Output Flag 0 (OF0) CRB Bit 0
When the ESSI is in Synchronous mode and transmitter 1 is disabled (TE1 = 0), the SC0
signal is configured as ESSI flag 0. If the serial control direction bit (SCD0) is set, the SC0
signal is an output. Data present in bit OF0 is written to SC0 at the beginning of the
frame in Normal mode or at the beginning of the next time slot in Network mode.
Bit OF0 is cleared by a hardware reset signal or by a software reset instruction.
7-20
DSP56305 User's Manual
MOTOROLA
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