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On-Chip Emulation Module
Pipeline Information and OGDBR
10.7.6
Software Request During Normal Activity
Upon executing the DSP56300 core instruction DEBUG (or DEBUGcc when the specified
condition is true), the chip enters the Debug mode after the instruction following the
DEBUG instruction has entered the instruction latch.
10.7.7
Enabling Trace Mode
When the Trace mode mechanism is enabled and the Trace Counter is greater than zero,
the Trace Counter is decremented after each instruction execution. Execution of an
instruction when the value in the Trace Counter is 0 causes the chip to enter the Debug
mode after completing the execution of the instruction. Only instructions actually
executed cause the Trace Counter to decrement. An aborted instruction does not
decrement the Trace Counter and does not cause the chip to enter the Debug mode.
10.7.8
Enabling Memory Breakpoints
When the memory breakpoint mechanism is enabled with a Breakpoint Counter value of
0, the chip enters the Debug mode after completing the execution of the instruction that
caused the memory breakpoint to occur. In case of breakpoints on executed Program
memory fetches, the breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on accesses to X, Y, or Program memory
spaces by MOVE instructions, the breakpoint is acknowledged after the completion of
the instruction following the instruction that accessed the specified address.
10.8
PIPELINE INFORMATION AND OGDBR
To restore the pipeline and to resume normal chip activity upon returning from the
Debug mode, a number of on-chip registers store the chip pipeline status. Figure 10-9
shows the block diagram of the Pipeline Information Registers, with the exception of the
PAB registers, which are shown in Figure 10-10 on page 10-22.
10-18
DSP56305 User's Manual
MOTOROLA
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