Essi Receive Enable (Re) Crb Bit 17 - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
ESSI Programming Model
Table 7-4 Mode and Signal Definition Table (Continued)
Control Bits
SYN TE0 TE1
Note:
CLK= Transmitter/Receiver Clock (Synchronous Operation)
CLKR= Receiver Clock
CLKT= Transmitter Clock
FS= Transmitter/Receiver Frame Sync (Synchronous Operation)
FSR= Receiver Frame Sync
FST= Transmitter Frame Sync
F0= Flag 0
F1= Flag 1 if SSC1 = 0
RD= Receive Data
TD0= Transmit Data signal 0
TD1= Transmit Data signal 1
TD2= Transmit Data signal 2
T0DE= Transmitter 0 drive enable if SYN = 1, TE2 = 0, SSC1 = 1, and SCD1 = 1
U= Unused (may be used as GPIO signal)
X=Don't Care
7.4.2.17

ESSI Receive Enable (RE) CRB Bit 17

When the RE bit is set, the receive portion of the ESSI is enabled. When this bit is cleared,
the receiver is disabled by inhibiting data transfer into RX. If data is being received while
this bit is cleared, the remainder of the word is shifted in and transferred to the ESSI
Receive Data Register.
RE must be set in both the Normal and On-demand modes for the ESSI to receive data.
In Network mode, clearing RE and setting it again disables the receiver after reception of
the current data word. The receiver remains disabled until the beginning of the next data
frame.
RE is cleared by either a hardware reset signal or a software reset instruction.
Note: The RE bit value does not affect frame sync generation.
7-32
TE2 RE SC0
DSP56305 User's Manual
ESSI Signals
SC1 SC2 SCK STD SRD
MOTOROLA