Motorola DSP56305 User Manual page 243

Table 6-18 Host Port Signals - Detailed Description (Sheet 3 of 13)
HI32
Port
PCI
a
Pin
HTRDY
Target Ready
Sustained tri-state bidirectional
d
signal.
Indicates the target agent's ability to
complete the current data phase of
HTRDY
the transaction.
HIRDY
conjunction with
phase is completed on any clock both
HIRDY HTRDY
and
asserted.
HTRDY
is asserted if:
• during a data read valid data
is present on HAD31-HAD0
(HRRQ = 1 in the HSTR).
• during a data write it
indicates the HI32 is ready to
accept data (HTRQ = 1 in the
HSTR).
• during a vector write it
indicates the HI32 is ready to
accept a new host command
(HC = 0 in the HCVR).
Wait cycles are inserted until both
HIRDY HTRDY
and
together.
HI32 Mode
Enhanced Universal
HDBEN
Host Data Bus Enable
Output signal.
Asserted during HI32 accesses.
When asserted the external (optional) data
transceiver outputs are enabled. When
is used in
deasserted the external transceiver outputs
. A data
are high impedance.
are sampled
are asserted
b
Universal
GPIO
PB20