Initialization; Decoder Mode; Figure 13-7 Viterbi Co-Processor In Encoder Mode - Motorola DSP56305 User Manual

VITERBI CO-PROCESSOR
Operating Modes
13.4.2 Encoder Mode
The Encoder mode is started by setting the ENCEN bit (VCRA Bit 3). Its functioning is
summarized in Figure 13-7.
During convolutional encoding the input data bits are encoded according to the rate,
constraint, and given tap polynomials as programmed. The bits to be encoded are
written one at a time to VDR as a hard value word ($800000 = 0 or $7FFF00 = 1). The
encoded bits (a symbol) are written to the output buffer (1023 × 1 bit RAM) The encoded
bits are read through the VDOR register. The number of VDOR reads per input bit varies
according to the rate, for instance: 2, 3, 4, 6 reads for 1/2, 1/3, 1/4, 1/6 rate, respectively,
given in a hard value format ($800000 for 0, or $7FFF00 for 1). The encoder operates at
the fixed rate of 1 input bit per 16 cycles.

Figure 13-7 Viterbi Co-Processor in Encoder Mode

13.4.2.1

Initialization

In order to initialize the starting state in the VCOP encoder, write the initial state IS[5:0]
in VTSR register, prior to starting the encoding operation.
13.4.3

Decoder Mode

The Decoder mode is started by setting the DECEN bit (VCRA Bit 2). Its functioning is
summarized in Figure 13-8.
The received stream of input symbols is supplied to the VCOP one symbol at a time
through the VDR FIFO (that is, sequential writes of symbol-bits combine to create a
symbol, written to VDR either by core or DMA). The branch metrics values based on that
symbol are calculated by the Branch Metric block.
The VCOP implements the convolutional decoder using a modified Viterbi algorithm
that can operate on soft-decision symbol inputs. The Manhattan metric system is used.
The decoder provides the Bit Error count (BER), the number of bits corrected by the
decoder. The BER is available to the DSP56300 core as the contents of the (read-only)
VBER.
13-12 DSP56305 User's Manual MOTOROLA