Self Configuration Mode - Motorola DSP56305 User Manual

IL7-IL0: These read/write bits are used to communicate PCI interrupt line routing
information. POST software will write the routing information into these bits as it
initializes and configures the PCI system.
The CILP cannot be accessed by the host when not in the PCI mode (HM≠$1).
The 24 most significant bits of the CILP register are hardwired and are not affected by
any type of reset. The personal hardware reset clears IL7-IL0.
6.7

SELF CONFIGURATION MODE

The Self Configuration mode is used to program the HI32 base address and HIRQ pulse
width, for operation in the Universal Bus mode; and for programming the configuration
registers for operation in a PCI environment without an external system configurator.
In the Self Configuration mode (HM = $5), the DSP56300 core can indirectly write to all
the writable HI32 configuration registers. The DSP56300 core writes the Dword data to
the AR bits of the DPMC and DPAR registers (the remaining bits in these registers are
ignored). The two most significant bytes of the Dword are written to the DPMC, the two
least significant, to the DPAR. The data is transferred to the configuration register by the
HI32 hardware. The registers are written sequentially beginning with the CSTR/CCMR
register (location $04). After each write to the DPAR, the data is transferred to the
accessed register and an internal pointer is advanced to point to the next Dword location
in the configuration space.
Note: At least one DSP instruction must appear between writing the Self
Configuration mode (HM2-HM0 = $5) and first write to the DPAR if the first
write is a one DSP clock cycle instruction. (e.g. move immediate and move
from external memory are more than one clock cycle)
MOTOROLA DSP56305 User's Manual
HOST INTERFACE (HI32)
SELF CONFIGURATION MODE
6-89