Hi32 Status Register (Hstr) - Motorola DSP56305 User Manual

HOST INTERFACE (HI32)
HOST SIDE Programming Model
6.6.2

HI32 Status Register (HSTR)

31 30 29 28
15 14 13 12
Reserved, read as zero and should be written zero
Bit
0
1
1
3-5
6
7
31-8
The HSTR is a 32-bit read-only status register used by the host processor to examine the
status and flags of the HI32.
When the HSTR is read to the PCI bus (HM=$1), the HAD31-HAD0 signals are driven
with the HSTR data during a read access.
In a 24-bit data Universal Bus mode (HM=$2 or $3 and HRF = $0), the HD23-HD0 signals
are driven with the three least significant HSTR bytes during a read access.
In a 16-bit data Universal Bus mode (HM=$2 or $3 and HRF≠$0), the HD15-HD0 signals
are driven with the two least significant bytes of the HSTR in a read access.
In PCI mode (HM = $1) memory space transactions, the HSTR is accessed if the PCI
address is HI32_base_address: $014.
When in a Universal Bus mode (HM=$2 or $3), the HSTR is accessed if the HA10-HA3
value matches the HI32 base address (CBMA, see Section 6.6.11) and the HA2-HA0
value is $5.
The status bits are described in the following paragraphs.
6-68
27 26 25 24
11 10 9 8
Name
TRDY Transmitter Ready
HTRQ Host Transmit Data Request
HRRQ Host Receive Data Request
HF5-HF3 Host Flags
HINT Host Interrupt A
HREQ Host Request
reserved
DSP56305 User's Manual
23 22 21 20
7 6 5 4
HREQ HINT HF5 HF4
Function
19 18 17 16
3 2 1 0
HF3 HRRQ HTRQ TRDY
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