Equalization Mode; Operating Modes - Motorola DSP56305 User Manual

24-bit digital signal processor
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VITERBI CO-PROCESSOR

Operating Modes

13.4
OPERATING MODES
The VCOP can be programmed to operate in the following modes:
• Equalization
• Encoder
• Decoder
• Memory Access
• Flush
Each operating mode has a data flow scheme associated with it.
There are also two states in which the VCOP is not functional:
• VCOP Individual Reset
• Idle
13.4.1

Equalization Mode

The Equalization mode is started by setting the EQEN bit (VCRA Bit 4). Its functioning is
summarized in Figure 13-6.
The received signal, which may have been corrupted by InterSymbol Interference (ISI) or
additive noise (AWGN), is equalized through the use of an MLSE equalizer. Ungerboeck
presented a type of MLSE equalizer employing a Matched Filter combined with a Viterbi
Algorithm section, for which a block diagram is given in Figure 13-2
equalizer output is hard decision (0,1) data bits. Soft data used as input to a Viterbi
decoder is proven to achieve similar results to the best alternative methods. The
equalizer should be supplied with the Viterbi parameters (VP) - the state transition
metrics for the equalization scheme, based on the linear combination of the channel
impulse response coefficients.
13-10
DSP56305 User's Manual
1
. The MLSE
MOTOROLA

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