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CYCLIC CODE CO-PROCESSOR
CCOP Programming Model
Input
Data
23 22 21 20
Bit
Select
Input
Data
Feedback Tap
Feedfwd Tap
Bit Select
Mask Tap
Figure 14-3 CFSR Configuration in the Parity Coding Modes
14.4
CCOP PROGRAMMING MODEL
The CCOP registers available to the programmer are shown in Table 14-1. All accessible
registers are mapped into the internal I/O memory space. These registers may be
accessed through regular MOVE instructions or by peripheral move (MOVEP)
instructions.
The registers are discussed in the following sections by functional block:
• Input/Output
– CCOP Data FIFO Register (CDFR)
• Count Register
– CCOP Count Register (CCNT)
• Step Function
– CCOP Step Function Select Register (CSFS),
– CCOP Step Function Table A (CSFTA),
14-6
17 16 15
14 13 12 11 10
19 18
Zero Detect
0001 0000 0000 0101 0010 0000
0000 0100 1000 0001 0000 0000
1111 1111 1111 0000 0000 0000
0000 0000 0000 0000 0000 0100
DSP56305 User's Manual
Feedback Tap
9
8
7
6
5
Feedfwd Tap
'0'
Mask
Tap
4
3
2
1
0
AA1302
MOTOROLA
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