Table 8-1 Word Formats; Sci Control Register (Scr); Word Select (Wds[0:2]) Scr Bits 0-2 - Motorola DSP56305 User Manual

8.3.1

SCI Control Register (SCR)

The SCI Control Register (SCR) is a 24-bit read/write register that controls the serial
interface operation. Seventeen of the twenty-four bits are currently defined. Each bit is
described in the following paragraphs.
8.3.1.1

Word Select (WDS[0:2]) SCR Bits 0-2

The word select WDS[0:2] bits select the format of transmitted and received data. Format
modes are listed in Table 8-1 and described in Figure 8-4.
WDS2 WDS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
The Asynchronous modes are compatible with most UART-type serial devices, and
support standard RS232C communication links. The Multidrop Asynchronous mode is
compatible with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051
serial interface. The Synchronous data mode is essentially a high-speed shift register
used for I/O expansion and stream-mode channel interfaces. Data synchronization is
accomplished by the use of a gated transmit and receive clock that is compatible with the
Intel 8051 serial interface mode 0.
MOTOROLA

Table 8-1 Word Formats

WDS0 Mode
0 0 8-Bit Synchronous Data (shift register mode)
1 1 Reserved
0 2 10-Bit Asynchronous (1 start, 8 data, 1 stop)
1 3 Reserved
0 4 11-Bit Asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1 5 11-Bit Asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
0 6 11-Bit Multidrop Asynchronous
(1 start, 8 data, 1 data type, 1 stop)
1 7 Reserved
DSP56305 User's Manual
Serial Communication Interface (SCI)
SCI Programming Model
Word Formats
8-9