Essi Exceptions; Essi Exception Types - Motorola DSP56305 User Manual

Enhanced Synchronous Serial Interface (ESSI)
Operating Modes
7.5.2

ESSI Exceptions

The ESSI can generate six different exceptions.
7.5.2.1

ESSI Exception Types

The ESSI exception types are discussed in the following paragraphs (ordered from the
highest to the lowest exception priority):
1. ESSI Receive Data with Exception Status
Occurs when the receive exception interrupt is enabled, the Receive Data Register
is full, and a receiver overrun error has occurred. This exception sets the ROE bit.
The ROE bit is cleared by first reading the SSISR and then reading RX.
2. ESSI Receive Data
Occurs when the receive interrupt is enabled, the Receive Data Register is full,
and no receive error conditions exist. Reading RX clears the pending interrupt.
This error-free interrupt can use a fast interrupt service routine for minimum
overhead.
3. ESSI Receive Last Slot Interrupt
Occurs when the ESSI is in Network mode and the last slot of the frame has
ended. This interrupt is generated regardless of the Receive Mask Register
setting. The receive last slot interrupt may be used to signal that the Receive Mask
Slot Register can be reset, the DMA channels may be reconfigured, and data
memory pointers may be reassigned. Using the receive last slot interrupt
guarantees that the previous frame was serviced with the previous setting and the
new frame will be serviced with the new setting without synchronization
problems.
Note: The maximum time it takes to service a receive last slot interrupt should not
exceed W – 1 ESSI bits service time (where W is the word length in bits).
4. ESSI Transmit Data with Exception Status
Occurs when the transmit exception interrupt is enabled, at least one Transmit
Data Register of the enabled transmitters is empty, and a transmitter underrun
error has occurred. This exception sets the TUE bit. The TUE bit is cleared by first
reading the SSISR and then writing to all the Transmit Data Registers of the
enabled transmitters, or by writing to the TSR to clear the pending interrupt.
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