Boundary Scan Register; Figure 11-3 Jtag Instruction Register - Motorola DSP56305 User Manual

11.3.1

Boundary Scan Register

The Boundary Scan Register (BSR) in the DSP56305 JTAG implementation contains bits
for all device signal and clock signals and associated control signals. All DSP56305
bidirectional signals have a single register bit in the BSR for signal data, and are
controlled by an associated control bit in the BSR. The DSP56305 BSR bit definitions are
described in Table 11-2.
11.3.2 Instruction Register
The DSP56305 JTAG implementation includes the three mandatory public instructions
(EXTEST, SAMPLE/PRELOAD, and BYPASS), and also supports the optional CLAMP
instruction defined by IEEE 1149.1. The HI-Z public instruction provides the capability
for disabling all device output drivers. The ENABLE_ONCE public instruction enables
the JTAG port to communicate with the OnCE circuitry. The DEBUG_REQUEST public
instruction enables the JTAG port to force the DSP56300 core into the Debug mode of
operation. The DSP56300 core includes a 4-bit instruction register without parity
consisting of a shift register with four parallel outputs. Data is transferred from the shift
register to the parallel outputs during the Update-IR controller state. Figure 11-3 shows
the JTAG Instruction Register.
The four bits are used to decode the eight unique instructions shown in Table 11-1. All
other encodings are reserved for future enhancements and are decoded as BYPASS.
MOTOROLA
JTAG Instruction
B3
Register (IR)

Figure 11-3 JTAG Instruction Register

DSP56305 User's Manual
B2 B1 B0
JTAG Port
TAP Controller
AA0746
11-7