Processing Done (Done)—Vstr Bit 5; Data Ready (Drdy)—Vstr Bit 6; End Stage (Estg)—Vstr Bit 7; Data Request (Dreq)—Vstr Bit 8 - Motorola DSP56305 User Manual

24-bit digital signal processor
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VITERBI CO-PROCESSOR
Programming Model
For the three major VCOP operating modes, the OPC bit is set:
• At encoding, after VCNT reaches zero, and the last symbol-bits word is read out
(via VDOR).
• At decoding, after VCNT reaches zero and flush operation is complete, when the
last data word has been read from the output buffer (via VDOR).
• At equalization, after VCNT reaches zero and flush operation completes, when
reading the last soft data (via VDOR ) is complete.
13.5.5.4
Processing Done (DONE)—VSTR Bit 5
The Processing Done(DONE) flag bit, when set, signals that the data block has finished
its processing (including the flush operation), resides in the output buffer, and is ready
to be transferred to the DSP56300 core. This bit is functional in decoding or equalization
modes (i.e. while CME bit in VCRB is cleared). The DONE bit is cleared after reading the
last word from the data output buffer (VDOR).
13.5.5.5
Data Ready (DRDY)—VSTR Bit 6
The Data Ready (DRDY) flag bit indicates, when set, that data is ready in VDOR. The bit
is functional in equalization, encoding, and decoding modes. The bit is cleared when the
VDOR register is read.
13.5.5.6
End Stage (ESTG)—VSTR Bit 7
The End Stage (ESTG) status bit indicates, when set, that the VCOP has finished all
operations of the current stage, including all piped operations. The bit is cleared
whenever 'stage update' (a pass over all states) begins.
13.5.5.7
Data Request (DREQ)—VSTR Bit 8
The Data Request (DREQ) flag bit indicates, when set, that new data is required for
processing. The bit is cleared when the VDR FIFO/register is written.
13.5.5.8
Data Output Buffer Full (DOBF)—VSTR Bit 9
The Data Output Buffer Full (DOBF) flag bit indicates, when set, that the output buffer
(VDOR) is full, causing processing to stop at the end of the current stage. The DOBF is
cleared by reading the VDOR register, thus enabling further processing.
13.5.5.9
Reserved Bits—VSTR Bits 2, 3, 10–15
These bits are reserved and should be written with zero.
13-24
DSP56305 User's Manual
MOTOROLA

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