Motorola DSP56305 User Manual page 207

24-bit digital signal processor
Table of Contents

Advertisement

In a Universal Bus mode (HM= $2 or $3):
• Fetch (SFT = 1):
There is no FIFO buffering of the DSP-to-host data path. Writing SFT = 1 resets the
DSP-to-host data path and clears the STRQ and the HRRQ. At the beginning of a
read data transfer from the HRXS, STRQ is set. STRQ is cleared when the
DSP56300 core writes to the DTXS; HRRQ is cleared if the HRXS is empty, and set
if it contains data to be read by an external host. If the host is not reading from the
HRXS, the DSP-to-host data path is forced to the reset and STRQ and HRRQ are
cleared.
Note:
Any data remaining in the DSP-to-host data path when entering the reset
state, is lost.
In both the PCI and Universal Bus modes (HM=$1, $2 or $3):
• Pre-fetch (SFT = 0):
The DSP-to-host data path is a six word deep (three word deep in the 32-bit data
format mode, HM = $1 and HRF = $0) FIFO buffer. STRQ reflects the status of the
DTXS and HRRQ reflects the status of the HRXS. STRQ is set if the DTXS is not
full, and cleared when the DSP56300 core fills the DTXS. HRRQ is cleared if the
HRXS is empty, and set when it contains data to be read by an external host.
The value of SFT may be changed only if the DTXS-HRXS data path is empty.
The personal hardware reset clears SFT.
6.6.1.6
Host Transmit Data Transfer Format (HTF1-HTF0) Bits 9 and 8
The HTF1-HTF0 bits define data transfer formats for host-to-DSP communication. The
data transfer format converter (HDTFC) operates according to the specified HTF1-HTF0
(see Table 6-15).
PCI host to DSP data transfer formats (HM = $1):
• If HTF = $0 (32-bit data mode):
All four PCI data bytes from HAD31-HAD0 signals are written to the 32-bit
HTXR. The two least significant bytes are transferred to the two least significant
bytes of the DRXR FIFO after which the two most significant bytes are transferred
to the two least significant bytes of the DRXR FIFO. Thus, when the DSP56300
core reads two words from the DRXR, the two least significant bytes of the first
word read contain the two least significant bytes of the 32-bit word written to the
HTXR, the two least significant bytes of the second word read contain the two
most significant bytes of the 32-bit word.
MOTOROLA
DSP56305 User's Manual
HOST INTERFACE (HI32)
HOST SIDE Programming Model
6-59

Advertisement

Table of Contents
loading

Table of Contents