Figure 14-1 Ccop Block Diagram; Cipher Mode Register Configuration; Ccop Block Diagram - Motorola DSP56305 User Manual

CYCLIC CODE CO-PROCESSOR

CCOP Block Diagram

14.3 CCOP BLOCK DIAGRAM
The CCOP architecture is shown in Figure 14-1.
PMB
Interface
Input Data Buffer
CFSR
Feedback Taps
Data FIFO Bank
Feedfwd Taps
Output Data Buffer
Bit Select
Mask Taps
Input Counter
8 × 4 bit
Step
Run Counter
Function
Table
Output Counter
Control
AA1300

Figure 14-1 CCOP Block Diagram

14.3.1

Cipher Mode Register Configuration

Figure 14-2 shows how the control register contents relate to CFSR configuration in the
Cipher modes.
14-4 DSP56305 User's Manual MOTOROLA