Motorola DSP56305 User Manual page 574

24-bit digital signal processor
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Equates
M_SSR
EQU
$FFFF93
M_SCCR
EQU
$FFFF9B
;
SCI Control Register Bit Flags
M_WDS
EQU
$7
M_WDS0
EQU
0
M_WDS1
EQU
1
M_WDS2
EQU
2
M_SSFTD
EQU
3
M_SBK
EQU
4
M_WAKE
EQU
5
M_RWU
EQU
6
M_WOMS
EQU
7
M_SCRE
EQU
8
M_SCTE
EQU
9
M_ILIE
EQU
10
M_SCRIE
EQU
11
M_SCTIE
EQU
12
M_TMIE
EQU
13
M_TIR
EQU
14
M_SCKP
EQU
15
M_REIE
EQU
16
;
SCI Status Register Bit Flags
M_TRNE
EQU
0
M_TDRE
EQU
1
M_RDRF
EQU
2
M_IDLE
EQU
3
M_OR
EQU
4
M_PE
EQU
5
M_FE
EQU
6
M_R8
EQU
7
;
SCI Clock Control Register
M_CD
EQU
$FFF
M_COD
EQU
12
M_SCP
EQU
13
M_RCM
EQU
14
M_TCM
EQU
15
;-----------------------------------------------------------------------
;
;
EQUATES for Synchronous Serial Interface (SSI)
;
;-----------------------------------------------------------------------
;
;
Register Addresses Of SSI0
B-6
; SCI Status Register
; SCI Clock Control Register
; Word Select Mask (WDS0-WDS3)
; Word Select 0
; Word Select 1
; Word Select 2
; SCI Shift Direction
; Send Break
; Wakeup Mode Select
; Receiver Wakeup Enable
; Wired-OR Mode Select
; SCI Receiver Enable
; SCI Transmitter Enable
; Idle Line Interrupt Enable
; SCI Receive Interrupt Enable
; SCI Transmit Interrupt Enable
; Timer Interrupt Enable
; Timer Interrupt Rate
; SCI Clock Polarity
; SCI Error Interrupt Enable (REIE)
; Transmitter Empty
; Transmit Data Register Empty
; Receive Data Register Full
; Idle Line Flag
; Overrun Error Flag
; Parity Error
; Framing Error Flag
; Received Bit 8 (R8) Address
; Clock Divider Mask (CD0-CD11)
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
DSP56305 User's Manual
MOTOROLA

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